Static random-access memory devices (SRAM) are well known and used extensively in semiconductor devices, such as complementary metal oxide semiconductors (CMOS). Static memories do not require periodic refresh signals in order to retain their stored data. The bit state in SRAM is stored in a pair of cross-coupled invertors, which form a circuit known as a flip-flop. The voltage on each of the two outputs of a flip-flop circuit is stable at only one of two possible voltage levels, because the operation of the circuit forces one output to a high potential, and the other to a low potential. The memory logic state of the cell is determined by whichever of the two inverter outputs is high. Flip-flops maintain a given state for as long as the circuit receives power, but they can be made to undergo a change in state (i.e., to flip), through the application of a trigger voltage of sufficient magnitude and duration to the appropriate input. Once the circuit has settled into its new stable state, the trigger voltage can be removed. SRAM cells can be implemented in NMOS, CMOS, bipolar or BICMOS technologies. For a more general background on this subject, see S. Wolf, Silicon Processing for the VLSI Era, Vols. I, II, and III, Latice Press, which are incorporated herein by reference.
The chief disadvantage of an SRAM cell is that it consists of at least six devices, as compared to only two for the dynamic-memory cell (DRAM). Thus, even when the same set of design rules is used, an SRAM chip cannot be built with as many cells as a DRAM chip in the same amount of area. One reason for the size of the SRAM is that separate openings or interconnect structures are used to connect to the silicon in the substrate and to the gate. Due to design rules, the interconnect structure must be a certain distance from the gate to prevent any possible short to the gate during the interconnects formation down to the silicon. These same design rules also cause the overall size of the SRAM cell to remain larger than desired.
On the other hand, SRAMs are the fastest semiconductor memories. Their speed is derived from the self-restoring nature of the flip-flop and the static peripheral circuits of the memory chip. Bipolar SRAMs are the fastest of all, and MOS SRAMs are the fastest among MOS memories.
Because of their speed, SRAMs use in devices that typically use DRAM cells is highly desirable. Unfortunately, however, it is also highly desirable to decrease the overall size of the device. Thus, conventionally designed SRAMs are often not used because the need for a smaller device outweighs the need for a faster device.
Accordingly, what is needed in the art is a device and method of manufacture thereof that provides a smaller SRAM cell. The device and method of the present invention address this need.